The present invention relates to inhibiting corrosion of metal plugs in an integrated circuit, which corrosion may occur during and after a chemical-mechanical polishing (CMP) process of the integrated circuit. More particularly, the present invention relates to using a corrosion inhibiting compound, such as a thiazole compound, during chemical-mechanical polishing (CMP) and/or after CMP to effectively inhibit metal plug corrosion.
Chemical mechanical polishing (sometimes referred to as "CMP") typically involves mounting a wafer face down on a holder and rotating the wafer face against a polishing pad mounted on a platen, which in turn is rotating or is in an orbital state. A slurry containing a chemical that chemically interacts with the facing wafer layer and an abrasive that physically removes that layer is flowed between the wafer and the polishing pad or on the pad near the wafer. In semiconductor wafer fabrication, this technique is commonly applied to planarize various wafer layers such as dielectric layers, metallization layers, etc.
A metal plug, typically a tungsten plug, is formed in a dielectric layer to provide a conductive pathway between a metallization layer and an underlying integrated circuit (IC) substrate layer and/or between two successive metallization layers disposed above the integrated circuit (IC) substrate. FIG. 1A shows a partially fabricated IC 10 that includes a tungsten layer 16, which is subjected to CMP to form tungsten plugs 26 as shown in FIG. 1B. CMP typically involves mounting a substrate face down on a holder and rotating the substrate face against a polishing pad mounted on a pallet, which in turn is rotating or is in orbital state. A slurry containing a chemical, e.g. an oxidizing agent such as ferric nitrate (Fe(NO.sub.3).sub.3), that chemically interacts with the tungsten layer and an abrasive, e.g. alumina (A1.sub.2 O.sub.3), that physically removes the tungsten layer, is flowed between the wafer and the polishing pad or on the pad near the substrate.
Referring to FIG. 1A, which shows partially fabricated IC 10 before the substrate surface undergoes CMP. A dielectric layer 12 disposed above a substrate surface 18 and having contact holes 14. A tungsten layer 16 is also disposed atop dielectric layer 12 and fills contact holes 14. Some significant steps involved in forming the partially fabricated IC of FIG. 1A include blanket depositing dielectric layer 12, such as SiO.sub.2, on substrate surface 18. After dielectric layer 12 is planarized, a masking layer (not shown), which typically includes photoresist, is blanket deposited over dielectric layer 12 and patterned by conventional photolithography. Next, the unmasked portions of dielectric layer 12 are etched to form contact holes 14 that provide an opening to the underlying substrate layer. After the masking layer is removed, tungsten layer 16 is blanket deposited over the substrate surface, filling contact holes 14 with tungsten. During metal deposition, a vertical "seam" structure 30 forms in the middle region of the contact hole that is filled with tungsten. Those skilled in the art will recognize that before the contact holes are filled with tungsten, they may be filled with a conductive titanium layer (not shown to simplify illustration) and a titanium nitride barrier layer (not shown to simplify illustration). Those skilled in the art will also recognize that vias may be similarly etched to provide an opening in a dielectric layer that is disposed between two metallization layers and that metal plugs may similarly be formed in such vias.
Next, tungsten layer 16 of partially fabricated IC 10 undergoes CMP, as described above, to form tungsten plugs by removing the tungsten layer deposited above the dielectric layer. Now referring to FIG. 1B, which shows a partially fabricated IC 20 after undergoing CMP. Partially fabricated IC has tungsten plugs 26 formed in a dielectric layer 12 disposed atop a substrate 18. During tungsten CMP, ferric nitrate (Fe(NO.sub.3).sub.3) oxidizes the tungsten to form tungsten oxide that is abraded by the alumina (A1.sub.2 O.sub.3) particles in the slurry. In this manner, the tungsten layer above the dielectric layer is removed to form tungsten plug 26 shown in FIG. 1B.
Unfortunately, during CMP, the slurry undesirably chemically attacks and opens up seam 30 (shown in FIG. 1A) of the tungsten plug, forming a "V-shaped" crack 30' in the middle region of the plug, as shown in FIG. 1B. This opening in the seam provides a pathway for the slurry, slurry residue and corrosive processing chemicals used in the post CMP cleaning steps to migrate or seep into the tungsten plug. After the crack side-walls have been exposed to these compounds for over a period of time, the tungsten plug corrodes, making the IC susceptible to catastrophic device failure.
What is therefore needed is an improved process, which effectively inhibits metal plug corrosion during the CMP process as well as after CMP, such as during post CMP cleaning steps.